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to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
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rev.3.00 feb 29, 2008 page 1 of 51 rej03b0117-0300 r8c/24 group, r8c/25 group single-chip 16-bit cmos mcu 1. overview these mcus are fabricated using a hi gh-performance silicon gate cmos proc ess, embedding the r8c/tiny series cpu core, and are packaged in a 52-pin molded-plastic lqfp or a 64-pin molded-plastic flga. it implements sophisticated instructions for a high level of instruction efficiency. with 1 mbyte of address space, they are capable of executing instructions at high speed. furthermore, the r8c/25 group has on-chip data flash (1 kb x 2 blocks). the difference between the r8c/24 grou p and r8c/25 group is only the presen ce or absence of data flash. their peripheral functions are the same. 1.1 applications electronic household appliances, office equipment, audio equipment, consumer products, etc. rej03b0117-0300 rev.3.00 feb 29, 2008
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 2 of 51 rej03b0117-0300 1.2 performance overview table 1.1 outlines the functions and specifications for r8c/24 group and table 1.2 outlines the functions and specifications for r8c/25 group. notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. specify the d version if d version functions are to be used. 3. please contact renesas technology sales offices for the y version. table 1.1 functions and specifications for r8c/24 group item specification cpu number of fundamental instructions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 2.2 to 5.5 v) operating mode single-chip address space 1 mbyte memory capacity refer to table 1.3 product inform ation for r8c/24 group peripheral functions ports i/o ports: 41 pins, input port: 3 pins led drive ports i/o ports: 8 pins timers timer ra: 8 bits 1 channel timer rb: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer rd: 16 bits 2 channels (input capture and output compare circuits) timer re: with real-time clock and compare match function serial interfaces 2 channels (uart0, uart1) clock synchronous serial i/o, uart clock synchronous serial interface 1 channel i 2 c bus interface (1) clock synchronous serial i/o with chip select lin module hardware lin: 1 channel (timer ra, uart0) a/d converter 10-bit a/d converter: 1 circuit, 12 channels watchdog timer 15 bits 1 channel (with prescaler) reset start selectable interrupts internal: 11 source s, external: 5 sources, software: 4 sources, priority levels: 7 levels clock clock generation circuits 3 circuits ? xin clock generation circuit (with on-chip feedback resistor) ? on-chip oscillator (h igh speed, low speed) high-speed on-chip osc illator has a frequency adjustment function ? xcin clock generation circuit (32 khz) real-time clock (timer re) oscillation stop de tection function xin clock oscillation stop detection function voltage detection circuit on-chip power-on reset circuit on-chip electrical characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) vcc = 2.2 to 5.5 v (f(xin) = 5 mhz) current consumption typ. 10 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 6 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 2.0 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz) typ. 0.7 a (vcc = 3.0 v, stop mode) flash memory programming and erasure voltage vcc = 2.7 to 5.5 v programming and erasure endurance 100 times operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (2) -20 to 105 c (y version) (3) package 52-pin molded-plastic lqfp 64-pin molded-plastic flga
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 3 of 51 rej03b0117-0300 table 1.2 functions and specifications for r8c/25 group notes: 1. i 2 c bus is a trademark of koninklijke philips electronics n. v. 2. specify the d version if d version functions are to be used. 3. please contact renesas technology sales offices for the y version. item specification cpu number of fundamental instructions 89 instructions minimum instruction execution time 50 ns (f(xin) = 20 mhz, vcc = 3.0 to 5.5 v) 100 ns (f(xin) = 10 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 2.2 to 5.5 v) operating mode single-chip address space 1 mbyte memory capacity refer to table 1.4 product inform ation for r8c/25 group peripheral functions ports i/o ports: 41 pins, input port: 3 pins led drive ports i/o ports: 8 pins timers timer ra: 8 bits 1 channel timer rb: 8 bits 1 channel (each timer equipped with 8-bit prescaler) timer rd: 16 bits 2 channels (input capture and output compare circuits) timer re: with real-time clock and compare match function serial interface 2 channels (uart0, uart1) clock synchronous serial i/o, uart clock synchronous serial interface 1 channel i 2 c bus interface (1) clock synchronous serial i/o with chip select lin module hardware lin: 1 cha nnel (timer ra, uart0) a/d converter 10-bit a/d converter: 1 circuit, 12 channels watchdog timer 15 bits 1 channel (with prescaler) reset start selectable interrupts internal: 11 source s, external: 5 sources, software: 4 sources, priority levels: 7 levels clock clock generation circuits 3 circuits ? xin clock generation circ uit (with on-chip feedback resistor) ? on-chip oscillator (h igh speed, low speed) high-speed on-chip osc illator has a frequency adjustment function ? xcin clock generation circuit (32 khz) real-time clock (timer re) oscillation stop de tection function xin clock oscillation stop detection function voltage detection circuit on-chip power-on reset circuit on-chip electrical characteristics supply voltage vcc = 3.0 to 5.5 v (f(xin) = 20 mhz) vcc = 2.7 to 5.5 v (f(xin) = 10 mhz) vcc = 2.2 to 5.5 v (f(xin) = 5 mhz) current consumption typ. 10 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 6 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 2.0 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz) typ. 0.7 a (vcc = 3.0 v, stop mode) flash memory programming and erasure voltage vcc = 2.7 to 5.5 v programming and erasure endurance 1,0000 times (data flash) 1,000 times (program rom) operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (2) -20 to 105 c (y version) (3) package 52-pin molded-plastic lqfp 64-pin molded-plastic flga
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 4 of 51 rej03b0117-0300 1.3 block diagram figure 1.1 shows a block diagram. figure 1.1 block diagram r8c/tiny series cpu core a/d converter (10 bits 12 channels) system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout uart or clock synchronous serial i/o (8 bits 2 channels) memory watchdog timer (15 bits) rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. i 2 c bus interface or clock synchronous serial i/o with chip select (8 bits 1 channel) 8 port p1 6 port p3 3 3 port p4 8 port p0 8 port p2 8 port p6 lin module (1 channel) timers timer ra (8 bits) timer rb (8 bits) timer rd (16 bits 2 channels) timer re (8 bits) peripheral functions
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 5 of 51 rej03b0117-0300 1.4 product information table 1.3 lists the product information for r8c/24 group and table 1.4 lists the product information for r8c/25 group. note: 1. the user rom is programmed before shipment. table 1.3 product information for r8c/24 group current of feb. 2008 type no. rom capacity ram capacity package type remarks r5f21244snfp 16 kbytes 1 kbyte plqp0052ja-a n version blank product r5f21245snfp 24 kbytes 2 kbytes plqp0052ja-a r5f21246snfp 32 kbytes 2 kbytes plqp0052ja-a r5f21247snfp 48 kbytes 2.5 kbytes plqp0052ja-a r5f21248snfp 64 kbytes 3 kbytes plqp0052ja-a r5f21244snlg 16 kbytes 1 kbyte ptlg0064ja-a r5f21246snlg 32 kbytes 2 kbytes ptlg0064ja-a r5f21244sdfp 16 kbytes 1 kbyte plqp0052ja-a d version blank product r5f21245sdfp 24 kbytes 2 kbytes plqp0052ja-a r5f21246sdfp 32 kbytes 2 kbytes plqp0052ja-a r5f21247sdfp 48 kbytes 2.5 kbytes plqp0052ja-a r5f21248sdfp 64 kbytes 3 kbytes plqp0052ja-a r5f21244snxxxfp 16 kbytes 1 kb yte plqp0052ja-a n version factory programming product (1) r5f21245snxxxfp 24 kbytes 2 kbytes plqp0052ja-a r5f21246snxxxfp 32 kbytes 2 kbytes plqp0052ja-a r5f21247snxxxfp 48 kbytes 2.5 kbytes plqp0052ja-a r5f21248snxxxfp 64 kbytes 3 kbytes plqp0052ja-a r5f21244snxxxlg 16 kbytes 1 kbyte ptlg0064ja-a r5f21246snxxxlg 32 kbytes 2 kbytes ptlg0064ja-a r5f21244sdxxxfp 16 kbytes 1 kb yte plqp0052ja-a d version factory programming product (1) r5f21245sdxxxfp 24 kbytes 2 kbytes plqp0052ja-a r5f21246sdxxxfp 32 kbytes 2 kbytes plqp0052ja-a r5f21247sdxxxfp 48 kbytes 2.5 kbytes plqp0052ja-a r5f21248sdxxxfp 64 kbytes 3 kbytes plqp0052ja-a
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 6 of 51 rej03b0117-0300 figure 1.2 type number, memory size, and package of r8c/24 group type no. r 5 f 21 24 6 s n xxx fp package type: fp: plqp0052ja-a (0.65 mm pin-pitch, 10 mm square body) lg: ptlg0064ja-a (0.65 mm pin-pitch, 6 mm square body) rom number classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c y: operating ambient temperature -20c to 105c (1) s: low-voltage version rom capacity 4: 16 kb 5: 24 kb 6: 32 kb 7: 48 kb 8: 64 kb r8c/24 group r8c/tiny series memory type f: flash memory renesas mcu renesas semiconductor note: 1. please contact renesas technology sales offices for the y version.
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 7 of 51 rej03b0117-0300 note: 1. the user rom is programmed before shipment. table 1.4 product information for r8c/25 group current of feb. 2008 type no. rom capacity ram capacity package type remarks program rom data flash r5f21254snfp 16 kbytes 1 kbyte 2 1 kbyte plqp0052ja-a n version blank product r5f21255snfp 24 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f21256snfp 32 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f21257snfp 48 kbytes 1 kbyte 2 2.5 kbytes plqp0052ja-a r5f21258snfp 64 kbytes 1 kbyte 2 3 kbytes plqp0052ja-a r5f21254snlg 16 kbytes 1 kbyte 2 1 kbyte ptlg0064ja-a r5f21256snlg 32 kbytes 1 kbyte 2 2 kbytes ptlg0064ja-a r5f21254sdfp 16 kbytes 1 kbyte 2 1 kbyte plqp0052ja-a d version blank product r5f21255sdfp 24 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f21256sdfp 32 kbytes 1 kbyte 2 2 kbytes plqp0052ja-a r5f21257sdfp 48 kbytes 1 kbyte 2 2.5 kbytes plqp0052ja-a r5f21258sdfp 64 kbytes 1 kbyte 2 3 kbytes plqp0052ja-a r5f21254snxxxfp 16 kbytes 1 kbyte 2 1 kbyte plqp0052ja-a n version factory programming product (1) r5f21255snxxxfp 24 kbytes 1 kbyt e 2 2 kbytes plqp0052ja-a r5f21256snxxxfp 32 kbytes 1 kbyt e 2 2 kbytes plqp0052ja-a r5f21257snxxxfp 48 kbytes 1 kbyt e 2 2.5 kbytes plqp0052ja-a r5f21258snxxxfp 64 kbytes 1 kbyt e 2 3 kbytes plqp0052ja-a r5f21254snxxxlg 16 kbytes 1 kbyt e 2 1 kbyte ptlg0064ja-a r5f21256snxxxlg 32 kbytes 1 kbyt e 2 2 kbytes ptlg0064ja-a r5f21254sdxxxfp 16 kbytes 1 kbyte 2 1 kbyte plqp0052ja-a d version factory programming product (1) r5f21255sdxxxfp 24 kbytes 1 kbyt e 2 2 kbytes plqp0052ja-a r5f21256sdxxxfp 32 kbytes 1 kbyt e 2 2 kbytes plqp0052ja-a r5f21257sdxxxfp 48 kbytes 1 kbyt e 2 2.5 kbytes plqp0052ja-a r5f21258sdxxxfp 64 kbytes 1 kbyt e 2 3 kbytes plqp0052ja-a
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 8 of 51 rej03b0117-0300 figure 1.3 type number, memory size, and package of r8c/25 group type no. r 5 f 21 25 6 s n xxx fp package type: fp: plqp0052ja-a (0.65 mm pin-pitch, 10 mm square body) lg: ptlg0064ja-a (0.65 mm pin-pitch, 6 mm square body) rom number classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c y: operating ambient temperature -20c to 105c (1) s: low-voltage version rom capacity 4: 16 kb 5: 24 kb 6: 32 kb 7: 48 kb 8: 64 kb r8c/25 group r8c/tiny series memory type f: flash memory renesas mcu renesas semiconductor note: 1. please contact renesas technology sales offices for the y version.
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 9 of 51 rej03b0117-0300 1.5 pin assignments figure 1.4 shows plqp0052ja-a pack age pin assignments (top view). figure 1.5 shows ptlg0064ja-a package pin assignments. figure 1.4 plqp0052ja-a package pin assignments (top view) 52 p3_7/sso pin assignments (top view) r8c/24 group r8c/25 group 51 p0_0/an7 50 p0_1/an6 49 p0_2/an5 48 p0_3/an4 47 p6_1 46 p6_2 45 p6_0/treo 44 p4_2/vref 43 p0_4/an3 42 p0_5/an2 41 p0_6/an1 12 11 10 9 8 7 6 5 4 3 2 1 13 14 15 16 17 18 19 20 21 22 23 24 25 p2_6/trdioc1 p1_7/traio/int1 p1_6/clk0 p1_5/rxd0/(traio)/(int1) (2) p1_4/txd0 p1_3/ki3/an11 p2_5/trdiob1 p2_4/trdioa1 p2_3/trdiod0 p2_2/trdioc0 p2_1/trdiob0 p2_0/trdioa0/trdclk 26 28 29 30 31 32 33 34 35 36 37 38 39 27 40 nc p2_7/trdiod1 vcc/avcc p4_6/xin vss/avss (1) xout/p4_7 reset p4_4/xcout p4_3/xcin mode p3_4/sda/scs p3_3/ssi p3_5/scl/ssck p3_1/trbo p3_0/trao p6_5/clk1 p6_4 p6_3 p0_7/an0 p4_5/int0 p6_6/int2/txd1 p6_7/int3/rxd1 p1_2/ki2/an10 p1_1/ki1/an9 p1_0/ki0/an8 nc nc nc notes: 1. p4_7 is an input-only port. 2. can be assigned to the pin in parentheses by a program. nc: non-connection package: plqp0052ja-a(52p6a-a) 0.65 mm pin pitch, 10 mm square body
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 10 of 51 rej03b0117-0300 figure 1.5 ptlg0064ja-a package pin assignments p2_6/ trdioc1 p2_5/ trdiob1 p2_2/ trdioc0 p1_7/traio/ int1 p1_6/clk0 p1_3/ki3/ an11 p4_5/int0 p6_7/int3/ rxd1 xin/p4_6 p2_3/ trdiod0 p2_0/trdioa0/ trdclk p1_4/txd0 p6_6/int2/ txd1 vss/avss p2_4/ trdioa1 p2_1/ trdiob0 p1_5/rxd0/ (traio)/(int1) (2) p1_2/ki2/ an10 p4_4/xcout p4_3/xcin p3_5/scl/ ssck p6_3 p0_6/an1 p0_7/an0 mode p3_7/sso p6_1 p0_4/an3 p0_5/an2 p3_1/trbo p3_4/sda/ scs p0_0/an7 p0_2/an5 p4_2/vref p3_0/trao p6_5/clk1 p0_1/an6 p0_3/an4 p6_2 p6_0/treo p6_4 p2_7/ trdiod1 vcc/avcc xout/ p4_7 (1) reset p1_0/ki0/ an8 p1_1/ki1/ an9 abcdefgh abcdefgh r5f21244s nlg japan pin assignments (top view) 50 48 46 45 nc 36 nc 4 51 49 nc 44 34 35 nc nc 5 52 47 43 42 nc 33 7 nc 6 2 37 nc 41 38 13 12 nc 9 8 32 31 nc nc 10 16 19 23 nc nc 30 nc 11 17 20 nc 24 28 nc 14 15 18 21 22 25 27 29 pin assignments (top perspective view) 3 p3_3/ssi 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 notes: 1. p4_7 is an input-only port. 2. can be assigned to the pin in parentheses by a program. 3. in the figure, the numbers in circles are the pin numbers of the 52-pin lqfp package (plqp0052ja-a). nc: non-connection package: ptlg0064ja-a(64f0g) 0.65 mm pin pitch, 6 mm square body
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 11 of 51 rej03b0117-0300 1.6 pin functions table 1.5 lists pin functions. i: input o: output i/o: input and output table 1.5 pin functions type symbol i/o type description power supply input vcc, vss i apply 2.2 v to 5. 5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss i power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provid ed for xin clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins. to use an external clock, input it to the xin pin and leave the xout pin open. xin clock output xout o xcin clock input xcin i these pins are provided for xcin clock generation circuit i/o. connect a crystal oscillator between the xcin and xcout pins. to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output xcout o int interrupt input int0 to int3 i int interrupt input pins. int0 is timer rd input pin. int1 is timer ra input pin. key input interrupt ki0 to ki3 i key input interrupt input pins timer ra traio i/o timer ra i/o pin trao o timer ra output pin timer rb trbo o timer rb output pin timer rd trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 i/o timer rd i/o ports trdclk i external clock input pin timer re treo o divided clock output pin serial interface clk0, clk1 i/o transfer clock i/o pin rxd0, rxd1 i serial data input pins txd0, txd1 o serial data output pins i 2 c bus interface scl i/o clock i/o pin sda i/o data i/o pin clock synchronous serial i/o with chip select ssi i/o data i/o pin scs i/o chip-select signal i/o pin ssck i/o clock i/o pin sso i/o data i/o pin reference voltage input vref i reference voltage input pin to a/d converter a/d converter an0 to an11 i analog input pins to a/d converter i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0, p3_1, p3_3 to p3_5, p3_7, p4_3 to p4_5, p6_0 to p6_7 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. p2_0 to p2_7 also function as led drive ports. input port p4_2, p4_6, p4_7 i input-only ports
r8c/24 group, r8c/25 group 1. overview rev.3.00 feb 29, 2008 page 12 of 51 rej03b0117-0300 note: 1. can be assigned to the pin in parentheses by a program. table 1.6 pin name information by pin number pin number control pin port i/o pin functions for of peripheral modules interrupt timer serial interface clock synchronous serial i/o with chip select i 2 c bus interface a/d converter 2 p3_5 ssck scl 3 p3_3 ssi 4 p3_4 scs sda 5mode 6 xcin p4_3 7 xcout p4_4 8 reset 9 xout p4_7 10 vss/avss 11 xin p4_6 12 vcc/avcc 13 p2_7 trdiod1 14 p2_6 trdioc1 15 p2_5 trdiob1 16 p2_4 trdioa1 17 p2_3 trdiod0 18 p2_2 trdioc0 19 p2_1 trdiob0 20 p2_0 trdioa0/trdclk 21 p1_7 int1 traio 22 p1_6 clk0 23 p1_5 (int1) (1) (traio) (1) rxd0 24 p1_4 txd0 25 p1_3 ki3 an11 27 p4_5 int0 int0 28 p6_6 int2 txd1 29 p6_7 int3 rxd1 30 p1_2 ki2 an10 31 p1_1 ki1 an9 32 p1_0 ki0 an8 33 p3_1 trbo 34 p3_0 trao 35 p6_5 clk1 36 p6_4 37 p6_3 38 p0_7 an0 41 p0_6 an1 42 p0_5 an2 43 p0_4 an3 44 vref p4_2 45 p6_0 treo 46 p6_2 47 p6_1 48 p0_3 an4 49 p0_2 an5 50 p0_1 an6 51 p0_0 an7 52 p3_7 sso
r8c/24 group, r8c/25 group 2. ce ntral processing unit (cpu) rev.3.00 feb 29, 2008 page 13 of 51 rej03b0117-0300 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1)
r8c/24 group, r8c/25 group 2. ce ntral processing unit (cpu) rev.3.00 feb 29, 2008 page 14 of 51 rej03b0117-0300 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is an alogous to a0. a1 can be comb ined with a0 and as a 32- bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register th at indicates the start address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp, and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation results in an overflow; otherwise to 0.
r8c/24 group, r8c/25 group 2. ce ntral processing unit (cpu) rev.3.00 feb 29, 2008 page 15 of 51 rej03b0117-0300 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupt are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt requ est is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interrupt priority le vels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined.
r8c/24 group, r8c/25 group 3. memory rev.3.00 feb 29, 2008 page 16 of 51 rej03b0117-0300 3. memory 3.1 r8c/24 group figure 3.1 is a memory map of r8c/24 group. the r8c/ 24 group has 1 mbyte of addr ess space from addresses 00000h to fffffh. the internal rom is allocated lower addresses, beginning with address 0ffffh. for example, a 48-kbyte internal rom area is allocated addresses 04000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal ram is allocated higher addresses, beginni ng with address 00400h. for example, a 2-kbyte internal ram area is allocated addresses 00400h to 00bffh. the inte rnal ram is used not only for storing data but also for calling subroutines and as stacks wh en interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresse s within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.1 memory map of r8c/24 group undefined instruction overflow brk instruction address match single step watchdog timer/oscillation stop detection/voltage monitor (reserved) (reserved) reset part number internal rom internal ram size address 0yyyyh r5f21244snfp, r5f21244snxxxfp, r5f21244sdfp, r5f21244sdxxxfp, r5f21244snlg, r5f21244snxxxlg r5f21245snfp, r5f21245snxxxfp, r5f21245sdfp, r5f21245sdxxxfp r5f21246snfp, r5f21246snxxxfp, r5f21246sdfp, r5f21246sdxxxfp, r5f21246snlg, r5f21246snxxxlg r5f21247snfp, r5f21247snxxxfp, r5f21247sdfp, r5f21247sdxxxfp r5f21248snfp, r5f21248snxxxfp, r5f21248sdfp, r5f21248sdxxxfp 16 kbytes 24 kbytes 32 kbytes 48 kbytes 64 kbytes ? ? ? ? 13fffh 007ffh 00bffh 00bffh 00dffh 00fffh 00400h 002ffh 00000h internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch address 0xxxxh note: 1. the blank regions are reserved. do not access locations in these regions. address 1zzzzh size 1 kbyte 2 kbytes 2 kbytes 2.5 kbytes 3 kbytes 0c000h 0a000h 08000h 04000h 04000h fffffh 0ffffh 0yyyyh internal rom (program rom) internal rom (program rom) 1zzzzh 0xxxh
r8c/24 group, r8c/25 group 3. memory rev.3.00 feb 29, 2008 page 17 of 51 rej03b0117-0300 3.2 r8c/25 group figure 3.2 is a memory map of r8c/25 group. the r8c/ 25 group has 1 mbyte of addr ess space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower ad dresses, beginning with a ddress 0ffffh. for example, a 48-kbyte internal rom area is allocated addresses 04000h to 0ffffh. the fixed interrupt vector table is al located addresses 0ffdch to 0ffffh. they store th e starting address of each interrupt routine. the internal rom (data flash) is allocated addresses 02400h to 02bffh. the internal ram area is allocated higher addresses, beginning with address 00400h. for example, a 2-kbyte internal ram is allocated addresses 00400h to 00bffh. th e internal ram is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. special function registers (sfrs) are allocated addresses 00000h to 002ffh. the peripheral function control registers are allocated here. all addresse s within the sfr, which have nothing allocated are reserved for future use and cannot be accessed by users. figure 3.2 memory map of r8c/25 group undefined instruction overflow brk instruction address match single step watchdog timer/oscillation stop detection/voltage monitor (reserved) (reserved) reset part number internal rom internal ram size address 0yyyyh r5f21254snfp, r5f21254snxxxfp, r5f21254sdfp, r5f21254sdxxxfp, r5f21254snlg, r5f21254snxxxlg r5f21255snfp, r5f21255snxxxfp, r5f21255sdfp, r5f21255sdxxxfp r5f21256snfp, r5f21256snxxxfp, r5f21256sdfp, r5f21256sdxxxfp, r5f21256snlg, r5f21256snxxxlg r5f21257snfp, r5f21257snxxxfp, r5f21257sdfp, r5f21257sdxxxfp r5f21258snfp, r5f21258snxxxfp, r5f21258sdfp, r5f21258sdxxxfp 16 kbytes 24 kbytes 32 kbytes 48 kbytes 64 kbytes 007ffh 00bffh 00bffh 00dffh 00fffh fffffh 0ffffh 0yyyyh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 0ffffh 0ffdch address 0xxxxh address 1zzzzh size 1 kbyte 2 kbytes 2 kbytes 2.5 kbytes 3 kbytes internal rom (data flash) (1) notes: 1. data flash block a (1 kbyte) and b (1 kbyte) are shown. 2. the blank regions are reserved. do not access locations in these regions. 0xxxxh 02400h 02bffh internal rom (program rom) 1zzzzh ? ? ? ? 13fffh 0c000h 0a000h 08000h 04000h 04000h
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 18 of 51 rej03b0117-0300 4. special function registers (sfrs) an sfr (special function regist er) is a control regist er for a peripheral function. ta bles 4.1 to 4.7 list the special function registers. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect this register. 3. the lvd0on bit in the ofs register is set to 1 and hardware reset. 4. power-on reset, voltage monitor 0 reset or the lvd0on bit in the ofs register is set to 0, and hardware reset. 5. software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect b2 and b3. 6. the csproini bit in the ofs register is set to 0. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 01101000b 0007h system clock control register 1 cm1 00100000b 0008h 0009h 000ah protect register prcr 00h 000bh 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdc 00x11111b 0010h address match interrupt register 0 rmad0 00h 0011h 00h 0012h 00h 0013h address match interrupt enable register aier 00h 0014h address match interrupt register 1 rmad1 00h 0015h 00h 0016h 00h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (6) 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h 0027h 0028h clock prescaler reset flag cpsrf 00h 0029h high-speed on-chip oscillator control register 4 fra4 when shipping 002ah 002bh high-speed on-chip oscillator control register 6 fra6 when shipping 002ch high-speed on-chip oscillator control register 7 fra7 when shipping 0030h 0031h voltage detection register 1 (2) vca1 00001000b 0032h voltage detection register 2 (2) vca2 00h (3) 00100000b (4) 0033h 0034h 0035h 0036h voltage monitor 1 circuit control register (5) vw1c 00001000b 0037h voltage monitor 2 circuit control register (5) vw2c 00h 0038h voltage monitor 0 circuit control register (2) vw0c 0000x000b (3) 0100x001b (4) 0039h 003ah 003eh 003fh
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 19 of 51 rej03b0117-0300 table 4.2 sfr information (2) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. selected by the iicsel bit in the pmr register. address register symbol after reset 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h timer rd0 interrupt control register trd0ic xxxxx000b 0049h timer rd1 interrupt control register trd1ic xxxxx000b 004ah timer re interrupt control register treic xxxxx000b 004bh 004ch 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu/iic interrupt control register (2) ssuic / iicic xxxxx000b 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h int2 interrupt control register int2ic xx00x000b 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh 005ch 005dh int0 interrupt control register int0ic xx00x000b 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 20 of 51 rej03b0117-0300 table 4.3 sfr information (3) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. selected by the iicsel bit in the pmr register. address register symbol after reset 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart1 transmit/receive mode register u1mr 00h 00a9h uart1 bit rate register u1brg xxh 00aah uart1 transmit buffer register u1tb xxh 00abh xxh 00ach uart1 transmit/receive control register 0 u1c0 00001000b 00adh uart1 transmit/receive control register 1 u1c1 00000010b 00aeh uart1 receive buffer register u1rb xxh 00afh xxh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h ss control register h / iic bus control register 1 (2) sscrh / iccr1 00h 00b9h ss control register l / iic bus control register 2 (2) sscrl / iccr2 0 1111101b 00bah ss mode register / iic bus mode register (2) ssmr / icmr 00011000b 00bbh ss enable register / iic bus interrupt enable register (2) sser / icier 00h 00bch ss status register / iic bus status register (2) sssr / icsr 00h / 0000x000b 00bdh ss mode register 2 / slave address register (2) ssmr2 / sar 00h 00beh ss transmit data register / iic bus transmit data register (2) sstdr / icdrt ffh 00bfh ss receive data register / iic bus receive data register (2) ssrdr / icdrr ffh
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 21 of 51 rej03b0117-0300 table 4.4 sfr information (4) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 00c0h a/d register ad xxh 00c1h xxh 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h a/d control register 2 adcon2 00h 00d5h 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h port p0 register p0 xxh 00e1h port p1 register p1 xxh 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h port p2 register p2 xxh 00e5h port p3 register p3 xxh 00e6h port p2 direction register pd2 00h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h 00eah port p4 direction register pd4 00h 00ebh 00ech port p6 register p6 xxh 00edh 00eeh port p6 direction register pd6 00h 00efh 00f0h 00f1h 00f2h 00f3h 00f4h port p2 drive capacity control register p2drr 00h 00f5h uart1 function select register u1sr xxh 00f6h 00f7h 00f8h port mode register pmr 00h 00f9h external input enable register inten 00h 00fah int input filter select register intf 00h 00fbh key input enable register kien 00h 00fch pull-up control register 0 pur0 00h 00fdh pull-up control register 1 pur1 xx00xx00b 00feh 00ffh
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 22 of 51 rej03b0117-0300 table 4.5 sfr information (5) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 00h 0119h timer re minute data register / compare data register tremin 00h 011ah timer re hour data register trehr 00h 011bh timer re day of week data register trewk 00h 011ch timer re control register 1 trecr1 00h 011dh timer re control register 2 trecr2 00h 011eh timer re count source select register trecsr 00001000b 011fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012ah 012bh 012ch 012dh 012eh 012fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h timer rd start register trdstr 11111100b 0138h timer rd mode register trdmr 00001110b 0139h timer rd pwm mode register trdpmr 10001000b 013ah timer rd function control register trdfcr 10000000b 013bh timer rd output master enable register 1 trdoer1 ffh 013ch timer rd output master enable register 2 trdoer2 0 1111111b 013dh timer rd output control register trdocr 00h 013eh timer rd digital filter function select register 0 trddf0 00h 013fh timer rd digital filter function select register 1 trddf1 00h
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 23 of 51 rej03b0117-0300 table 4.6 sfr information (6) (1) x: undefined note: 1. the blank regions are reserved. do not access locations in these regions. address register symbol after reset 0140h timer rd control register 0 trdcr0 00h 0141h timer rd i/o control register a0 trdiora0 10001000b 0142h timer rd i/o control register c0 trdiorc0 10001000b 0143h timer rd status register 0 trdsr0 11100000b 0144h timer rd interrupt enable register 0 trdier0 11100000b 0145h timer rd pwm mode output level control register 0 trdpocr0 1111 1000b 0146h timer rd counter 0 trd0 00h 0147h 00h 0148h timer rd general register a0 trdgra0 ffh 0149h ffh 014ah timer rd general register b0 trdgrb0 ffh 014bh ffh 014ch timer rd general register c0 trdgrc0 ffh 014dh ffh 014eh timer rd general register d0 trdgrd0 ffh 014fh ffh 0150h timer rd control register 1 trdcr1 00h 0151h timer rd i/o control register a1 trdiora1 10001000b 0152h timer rd i/o control register c1 trdiorc1 10001000b 0153h timer rd status register 1 trdsr1 11000000b 0154h timer rd interrupt enable register 1 trdier1 11100000b 0155h timer rd pwm mode output level control register 1 trdpocr1 1111 1000b 0156h timer rd counter 1 trd1 00h 0157h 00h 0158h timer rd general register a1 trdgra1 ffh 0159h ffh 015ah timer rd general register b1 trdgrb1 ffh 015bh ffh 015ch timer rd general register c1 trdgrc1 ffh 015dh ffh 015eh timer rd general register d1 trdgrd1 ffh 015fh ffh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh
r8c/24 group, r8c/25 group 4. spec ial function registers (sfrs) rev.3.00 feb 29, 2008 page 24 of 51 rej03b0117-0300 table 4.7 sfr information (7) (1) x: undefined notes: 1. the blank regions are reserved. do not access locations in these regions. 2. the ofs register cannot be changed by a pr ogram. use a flash programmer to write to it. address register symbol after reset 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018ah 018bh 018ch 018dh 018eh 018fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019ah 019bh 019ch 019dh 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h 01b3h flash memory control register 4 fmr4 01000000b 01b4h 01b5h flash memory control register 1 fmr1 1000000xb 01b6h 01b7h flash memory control register 0 fmr0 00000001b 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh ffffh option function select register ofs (note 2)
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 25 of 51 rej03b0117-0300 5. electrical characteristics note: 1. 300 mw for the ptlg0064ja-a package. table 5.1 absolute maximum ratings symbol parameter condition rated value unit v cc /av cc supply voltage -0.3 to 6.5 v v i input voltage -0.3 to v cc + 0.3 v v o output voltage -0.3 to v cc + 0.3 v p d power dissipation t opr = 25 c 500 (1) mw t opr operating ambient temperature -20 to 85 (n version) / -40 to 85 (d version) c t stg storage temperature -65 to 150 c the electrical characteristics of n version (topr = -20 to 85 c) and d version (topr = -40 to 85 c) are listed below. please contact renesas technology sales offices for the electrical characteristics in the y version (topr = -20 to 105 c).
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 26 of 51 rej03b0117-0300 notes: 1. v cc = 2.2 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. the average output current indicates the av erage value of current measured during 100 ms. table 5.2 recommended operating conditions symbol parameter conditions standard unit min. typ. max. v cc /av cc supply voltage 2.2 ? 5.5 v v ss /av ss supply voltage ? 0 ? v v ih input ?h? voltage 0.8 v cc ? v cc v v il input ?l? voltage 0 ? 0.2 v cc v i oh(sum) peak sum output ?h? current sum of all pins i oh(peak) ?? -160 ma i oh(sum) average sum output ?h? current sum of all pins i oh(avg) ?? -80 ma i oh(peak) peak output ?h? current except p2_0 to p2_7 ?? -10 ma p2_0 to p2_7 ?? -40 ma i oh(avg) average output ?h? current except p2_0 to p2_7 ?? -5 ma p2_0 to p2_7 ?? -20 ma i ol(sum) peak sum output ?l? current sum of all pins i ol(peak) ?? 160 ma i ol(sum) average sum output ?l? current sum of all pins i ol(avg) ?? 80 ma i ol(peak) peak output ?l? current except p2_0 to p2_7 ?? 10 ma p2_0 to p2_7 ?? 40 ma i ol(avg) average output ?l? current except p2_0 to p2_7 ?? 5ma p2_0 to p2_7 ?? 20 ma f (xin) xin clock input oscillation frequency 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz f (xcin) xcin clock input oscillation frequency 2.2 v v cc 5.5 v 0 ? 70 khz ? system clock ocd2 = 0 xln clock selected 3.0 v v cc 5.5 v 0 ? 20 mhz 2.7 v v cc < 3.0 v 0 ? 10 mhz 2.2 v v cc < 2.7 v 0 ? 5mhz ocd2 = 1 on-chip oscillator clock selected fra01 = 0 low-speed on-chip oscillator clock selected ? 125 ? khz fra01 = 1 high-speed on-chip oscillator clock selected 3.0 v v cc 5.5 v ?? 20 mhz fra01 = 1 high-speed on-chip oscillator clock selected 2.7 v v cc 5.5 v ?? 10 mhz fra01 = 1 high-speed on-chip oscillator clock selected 2.2 v v cc 5.5 v ?? 5mhz
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 27 of 51 rej03b0117-0300 notes: 1. av cc = 2.2 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. when the analog input voltage is over the reference voltage, the a/d conversion result will be 3ffh in 10-bit mode and ffh in 8-bit mode. figure 5.1 ports p0 to p4, p6 timing measurement circuit table 5.3 a/d converter characteristics symbol parameter conditions standard unit min. typ. max. ? resolution v ref = av cc ?? 10 bit ? absolute accuracy 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 3 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v ?? 2 lsb 10-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 5 lsb 8-bit mode ad = 10 mhz, v ref = av cc = 3.3 v ?? 2 lsb 10-bit mode ad = 5 mhz, v ref = av cc = 2.2 v ?? 5 lsb 8-bit mode ad = 5 mhz, v ref = av cc = 2.2 v ?? 2 lsb r ladder resistor ladder v ref = av cc 10 ? 40 k ? t conv conversion time 10-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 3.3 ?? s 8-bit mode ad = 10 mhz, v ref = av cc = 5.0 v 2.8 ?? s v ref reference voltage 2.2 ? av cc v v ia analog input voltage (2) 0 ? av cc v ? a/d operating clock frequency without sample and hold v ref = av cc = 2.7 to 5.5 v 0.25 ? 10 mhz with sample and hold v ref = av cc = 2.7 to 5.5 v 1 ? 10 mhz without sample and hold v ref = av cc = 2.2 to 5.5 v 0.25 ? 5mhz with sample and hold v ref = av cc = 2.2 to 5.5 v 1 ? 5mhz p0 p1 p2 p3 p4 p6 30pf
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 28 of 51 rej03b0117-0300 notes: 1. v cc = 2.7 to 5.5 v at t opr = 0 to 60 c, unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 7. the data hold time includes time that the power supply is off or the clock is not supplied. table 5.4 flash memory (program rom) electrical characteristics symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) r8c/24 group 100 (3) ?? times r8c/25 group 1,000 (3) ?? times ? byte program time ? 50 400 s ? block erase time ? 0.4 9 s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature 0 ? 60 c ? data hold time (7) ambient temperature = 55 c20 ?? year
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 29 of 51 rej03b0117-0300 notes: 1. v cc = 2.7 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. definition of programming/erasure endurance the programming and erasure endurance is defined on a per-block basis. if the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. for example, if 1,024 1-byte writes are performed to block a, a 1 kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. however, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. endurance to guarantee all electrical characteristics after program and erase. (1 to min. value can be guaranteed). 4. standard of block a and block b when program and erase endurance exceeds 1,000 times. byte program time to 1,000 times is the same as that in program rom. 5. in a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possib le is used up before performing an erase operation. for example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. it is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. if an error occurs during block erase, attempt to execute t he clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. customers desiring program/erase failure rate information should contact their renesas te chnical support representative. 8. -40 c for d version. 9. the data hold time includes time that the po wer supply is off or the clock is not supplied. table 5.5 flash memory (data flash block a, block b) electrical characteristics (4) symbol parameter conditions standard unit min. typ. max. ? program/erase endurance (2) 10,000 (3) ?? times ? byte program time (program/erase endurance 1,000 times) ? 50 400 s ? byte program time (program/erase endurance > 1,000 times) ? 65 ? s ? block erase time (program/erase endurance 1,000 times) ? 0.2 9 s ? block erase time (program/erase endurance > 1,000 times) ? 0.3 ? s t d(sr-sus) time delay from suspend request until suspend ?? 97+cpu clock 6 cycles s ? interval from erase start/restart until following suspend request 650 ?? s ? interval from program start/restart until following suspend request 0 ?? ns ? time from suspend until program/erase restart ?? 3+cpu clock 4 cycles s ? program, erase voltage 2.7 ? 5.5 v ? read voltage 2.2 ? 5.5 v ? program, erase temperature -20 (8) ? 85 c ? data hold time (9) ambient temperature = 55 c20 ?? year
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 30 of 51 rej03b0117-0300 figure 5.2 time delay until suspend notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version). 2. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca25 bit in the vca2 register to 0. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version). 2. time until the voltage monitor 1 interrupt request is generated after the voltage passes v det1 . 3. necessary time until the voltage detection circuit operates when setting to 1 again after setting the vca26 bit in the vca2 register to 0. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version). 2. time until the voltage monitor 2 interrupt request is generated after the voltage passes v det2 . 3. necessary time until the voltage detection circuit operates after setting to 1 again af ter setting the vca27 bit in the vca2 register to 0. table 5.6 voltage detection 0 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det0 voltage detection level 2.2 2.3 2.4 v ? voltage detection circuit self power consumption vca25 = 1, v cc = 5.0 v ? 0.9 ? a t d(e-a) waiting time until voltage detection circuit operation starts (2) ?? 300 s vccmin mcu operating voltage minimum value 2.2 ?? v table 5.7 voltage detection 1 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det1 voltage detection level 2.70 2.85 3.00 v ? voltage monitor 1 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca26 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s table 5.8 voltage detection 2 circuit electrical characteristics symbol parameter condition standard unit min. typ. max. v det2 voltage detection level 3.3 3.6 3.9 v ? voltage monitor 2 interrupt request generation time (2) ? 40 ? s ? voltage detection circuit self power consumption vca27 = 1, v cc = 5.0 v ? 0.6 ? a t d(e-a) waiting time until voltage detection circuit operation starts (3) ?? 100 s fmr46 suspend request (maskable interrupt request) fixed time t d(sr-sus) clock-dependent time access restart
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 31 of 51 rej03b0117-0300 notes: 1. the measurement condition is t opr = -20 to 85 ?? ? ??
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 32 of 51 rej03b0117-0300 notes: 1. v cc = 2.2 to 5.5 v, t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. standard values when the fra1 register value after reset is assumed. 3. standard values when the corrected value of the fra6 register has been written to the fra1 register. 4. this enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in uart mode. note: 1. v cc = 2.2 to 5.5 v, t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. notes: 1. the measurement condition is v cc = 2.2 to 5.5 v and t opr = 25 c. 2. waiting time until the internal power s upply generation circuit stabilizes during power-on. 3. time until system clock supply starts after the interrupt is acknowledged to exit stop mode. table 5.10 high-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco40m high-speed on-chip oscillator frequency temperature ? supply voltage dependence v cc = 4.75 to 5.25 v 0 c t opr 60 c (2) 39.2 40 40.8 mhz v cc = 4.5 to 5.5 v -20 c t opr 85 c 38.8 40 40.8 mhz v cc = 4.5 to 5.5 v -40 c t opr 85 c 38.4 40 40.8 mhz v cc = 3.0 to 5.5 v -20 c t opr 85 c (2) 38.8 40 41.2 mhz v cc = 3.0 to 5.5 v -40 c t opr 85 c (2) 38.4 40 41.6 mhz v cc = 2.7 to 5.5 v -20 c t opr 85 c (2) 38 40 42 mhz v cc = 2.7 to 5.5 v -40 c t opr 85 c (2) 37.6 40 42.4 mhz v cc = 2.2 to 5.5 v -20 c t opr 85 c (3) 35.2 40 44.8 mhz v cc = 2.2 to 5.5 v -40 c t opr 85 c (3) 34 40 46 mhz high-speed on-chip oscillator frequency when correction value in fra7 register is written to fra1 register (4) v cc = 5.0 v, t opr = 25 c ? 36.864 mhz v cc = 3.0 to 5.5 v -20 c t opr 85 c -3% ? 3% % ? value in fra1 register after reset 08h ? f7h ? ? oscillation fr equency adjustment unit of high- speed on-chip oscillator adjust fra1 register (value after reset) to -1 ? +0.3 ? mhz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 400 ? a table 5.11 low-speed on-chip oscillator circuit electrical characteristics symbol parameter condition standard unit min. typ. max. foco-s low-speed on-chip oscillator frequency 30 125 250 khz ? oscillation st ability time ? 10 100 s ? self power consumption at oscillation v cc = 5.0 v, t opr = 25 c ? 15 ? a table 5.12 power supply circuit timing characteristics symbol parameter condition standard unit min. typ. max. t d(p-r) time for internal power supply stabilization during power-on (2) 1 ? 2000 s t d(r-s) stop exit time (3) ?? 150 s
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 33 of 51 rej03b0117-0300 notes: 1. v cc = 2.2 to 5.5 v, v ss = 0 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) table 5.13 timing requirements of clock synchronous serial i/o with chip select (1) symbol parameter conditions standard unit min. typ. max. t sucyc ssck clock cycle time 4 ?? t cyc (2) t hi ssck clock ?h? width 0.4 ? 0.6 t sucyc t lo ssck clock ?l? width 0.4 ? 0.6 t sucyc t rise ssck clock rising time master ?? 1 t cyc (2) slave ?? 1 s t fall ssck clock falling time master ?? 1 t cyc (2) slave ?? 1 s t su sso, ssi data input setup time 100 ?? ns t h sso, ssi data input hold time 1 ?? t cyc (2) t lead scs setup time slave 1t cyc + 50 ?? ns t lag scs hold time slave 1t cyc + 50 ?? ns t od sso, ssi data output delay time ?? 1 t cyc (2) t sa ssi slave access time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 2.2 v v cc < 2.7 v ?? 1.5t cyc + 200 ns t or ssi slave out open time 2.7 v v cc 5.5 v ?? 1.5t cyc + 100 ns 2.2 v v cc < 2.7 v ?? 1.5t cyc + 200 ns
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 34 of 51 rej03b0117-0300 figure 5.4 i/o timing of clock synchronous serial i/o with chip select (master) v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t od t h t su scs (output) ssck (output) (cpos = 1) ssck (output) (cpos = 0) sso (output) ssi (input) 4-wire bus communication mode, master, cphs = 0 cphs, cpos: bits in ssmr register
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 35 of 51 rej03b0117-0300 figure 5.5 i/o timing of clock synchronous serial i/o with chip select (slave) v ih or v oh v ih or v oh scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 1 v ih or v oh v ih or v oh t hi t lo t hi t fall t rise t lo t sucyc t h t su scs (input) ssck (input) (cpos = 1) ssck (input) (cpos = 0) sso (input) ssi (output) 4-wire bus communication mode, slave, cphs = 0 t od t lead t sa t lag t or t hi t lo t hi t fall t rise t lo t sucyc t h t su t od t lead t sa t lag t or cphs, cpos: bits in ssmr register
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 36 of 51 rej03b0117-0300 figure 5.6 i/o timing of clock synchronous serial i/o with chip select (clock synchronous communication mode) v ih or v oh t hi t lo t sucyc t od t h t su ssck sso (output) ssi (input) v ih or v oh
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 37 of 51 rej03b0117-0300 notes: 1. v cc = 2.2 to 5.5 v, v ss = 0 v and t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified. 2. 1t cyc = 1/f1(s) figure 5.7 i/o timing of i 2 c bus interface table 5.14 timing requirements of i 2 c bus interface (1) symbol parameter condition standard unit min. typ. max. t scl scl input cycle time 12t cyc + 600 (2) ?? ns t sclh scl input ?h? width 3t cyc + 300 (2) ?? ns t scll scl input ?l? width 5t cyc + 500 (2) ?? ns t sf scl, sda input fall time ?? 300 ns t sp scl, sda input spike pulse rejection time ?? 1t cyc (2) ns t buf sda input bus-free time 5t cyc (2) ?? ns t stah start condition input hold time 3t cyc (2) ?? ns t stas retransmit start condition input setup time 3t cyc (2) ?? ns t stop stop condition input setup time 3t cyc (2) ?? ns t sdas data input setup time 1t cyc + 20 (2) ?? ns t sdah data input hold time 0 ?? ns sda t stah t scll t buf v ih v il t sclh scl t sr t sf t sdah t scl t stas t sp t stop t sdas p (2) s (1) sr (3) p (2) notes: 1. start condition 2. stop condition 3. retransmit start condition
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 38 of 51 rej03b0117-0300 note: 1. v cc = 4.2 to 5.5 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), f(xin) = 20 mhz, unless otherwise specified. table 5.15 electrical characteristics (1) [v cc = 5 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p2_0 to p2_7, xout i oh = -5 ma v cc ? 2.0 ? v cc v i oh = -200 av cc ? 0.5 ? v cc v p2_0 to p2_7 drive capacity high i oh = -20 ma v cc ? 2.0 ? v cc v drive capacity low i oh = -5 ma v cc ? 2.0 ? v cc v xout drive capacity high i oh = -1 ma v cc ? 2.0 ? v cc v drive capacity low i oh = -500 av cc ? 2.0 ? v cc v v ol output ?l? voltage except p2_0 to p2_7, xout i ol = 5 ma ?? 2.0 v i ol = 200 a ?? 0.45 v p2_0 to p2_7 drive capacity high i ol = 20 ma ?? 2.0 v drive capacity low i ol = 5 ma ?? 2.0 v xout drive capacity high i ol = 1 ma ?? 2.0 v drive capacity low i ol = 500 a ?? 2.0 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.1 0.5 ? v reset 0.1 1.0 ? v i ih input ?h? current vi = 5 v, vcc = 5v ?? 5.0 a i il input ?l? current vi = 0 v, vcc = 5v ?? -5.0 a r pullup pull-up resistance vi = 0 v, vcc = 5v 30 50 167 k ? r fxin feedback resistance xin ? 1.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 39 of 51 rej03b0117-0300 table 5.16 electrical characteristics (2) [vcc = 5 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 10 17 ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 915ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 20 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 5 ? ma xin = 16 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma high-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 20 mhz low-speed on-chip oscillator on = 125 khz no division ? 10 15 ma xin clock off high-speed on-chip oscillator on foco = 20 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 4 ? ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 5.5 10 ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2.5 ? ma low-speed on-chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 130 300 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 30 ? a
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 40 of 51 rej03b0117-0300 table 5.17 electrical characteristics (3) [vcc = 5 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 3.3 to 5.5 v) single-chip mode, output pins are open, other pins are v ss wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 75 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 60 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 4.0 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 2.2 ? a increase during a/d converter operation without sample & hold ? 2.6 ? ma with sample & hold ? 1.6 ? ma stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.8 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.2 ? a
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 41 of 51 rej03b0117-0300 timing requirements (unless otherwise specified: v cc = 5 v, v ss = 0 v at topr = 25 c) [v cc = 5 v] figure 5.8 xin input and xcin input timing diagram when v cc = 5 v figure 5.9 traio input timing diagram when v cc = 5 v table 5.18 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 50 ? ns t wh(xin) xin input ?h? width 25 ? ns t wl(xin) xin input ?l? width 25 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.19 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 100 ? ns t wh(traio) traio input ?h? width 40 ? ns t wl(traio) traio input ?l? width 40 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 5 v xcin input t wh(xcin) t c(xcin) t wl(xcin) traio input v cc = 5 v t c(traio) t wl(traio) t wh(traio)
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 42 of 51 rej03b0117-0300 i = 0 or 1 figure 5.10 serial interface timing diagram when v cc = 5 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.11 external interrupt inti input timing diagram when v cc = 5 v table 5.20 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 200 ? ns t w(ckh) clki input ?h? width 100 ? ns t w(ckl) clki input ?l? width 100 ? ns t d(c-q) txdi output delay time ? 50 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 50 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.21 external interrupt inti (i = 0 to 3) input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 250 (1) ? ns t w(inl) int0 input ?l? width 250 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi i = 0 or 1 v cc = 5 v inti input t w(inl) t w(inh) i = 0 to 3 v cc = 5 v
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 43 of 51 rej03b0117-0300 note: 1. v cc =2.7 to 3.3 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), f(xin) = 10 mh z, unless otherwise specified. table 5.22 electrical characteristics (3) [v cc = 3 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p2_0 to p2_7, xout i oh = -1 ma v cc - 0.5 ? v cc v p2_0 to p2_7 drive capacity high i oh = -5 ma v cc - 0.5 ? v cc v drive capacity low i oh = -1 ma v cc - 0.5 ? v cc v xout drive capacity high i oh = -0.1 ma v cc - 0.5 ? v cc v drive capacity low i oh = -50 av cc - 0.5 ? v cc v v ol output ?l? voltage except p2_0 to p2_7, xout i ol = 1 ma ?? 0.5 v p2_0 to p2_7 drive capacity high i ol = 5 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.1 0.3 ? v reset 0.1 0.4 ? v i ih input ?h? current vi = 3 v, vcc = 3v ?? 4.0 a i il input ?l? current vi = 0 v, vcc = 3v ?? -4.0 a r pullup pull-up resistance vi = 0 v, vcc = 3v 66 160 500 k ? r fxin feedback resistance xin ? 3.0 ? m ? r fxcin feedback resistance xcin ? 18 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 44 of 51 rej03b0117-0300 table 5.23 electrical characteristics (4) [vcc = 3 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.7 to 3.3 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 6 ? ma xin = 10 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma high-speed on- chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz no division ? 59ma xin clock off high-speed on-chip oscillator on foco = 10 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 2 ? ma low-speed on- chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 130 300 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 130 300 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 30 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 25 70 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 23 55 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.8 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 2.0 ? a increase during a/d converter operation without sample & hold ? 0.9 ? ma with sample & hold ? 0.5 ? ma stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.7 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.1 ? a
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 45 of 51 rej03b0117-0300 timing requirements (unless otherwise specified: v cc = 3 v, v ss = 0 v at topr = 25 c) [v cc = 3 v] figure 5.12 xin input and xcin input timing diagram when v cc = 3 v figure 5.13 traio input timing diagram when v cc = 3 v table 5.24 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 100 ? ns t wh(xin) xin input ?h? width 40 ? ns t wl(xin) xin input ?l? width 40 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.25 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 300 ? ns t wh(traio) traio input ?h? width 120 ? ns t wl(traio) traio input ?l? width 120 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 3 v xcin input t wh(xcin) t c(xcin) t wl(xcin) traio input v cc = 3 v t c(traio) t wl(traio) t wh(traio)
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 46 of 51 rej03b0117-0300 i = 0 or 1 figure 5.14 serial interface timing diagram when v cc = 3 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.15 external interrupt inti input timing diagram when v cc = 3 v table 5.26 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 300 ? ns t w(ckh) clki input ?h? width 150 ? ns t w(ckl) clki input ?l? width 150 ? ns t d(c-q) txdi output delay time ? 80 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 70 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.27 external interrupt inti (i = 0 to 3) input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 380 (1) ? ns t w(inl) int0 input ?l? width 380 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 3 v i = 0 or 1 inti input t w(inl) t w(inh) v cc = 3 v i = 0 to 3
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 47 of 51 rej03b0117-0300 note: 1. v cc = 2.2 v at t opr = -20 to 85 c (n version) / -40 to 85 c (d version), f(xin) = 5 mh z, unless otherwise specified. table 5.28 electrical characteristics (5) [v cc = 2.2 v] symbol parameter condition standard unit min. typ. max. v oh output ?h? voltage except p2_0 to p2_7, xout i oh = -1 ma v cc - 0.5 ? v cc v p2_0 to p2_7 drive capacity high i oh = -2 ma v cc - 0.5 ? v cc v drive capacity low i oh = -1 ma v cc - 0.5 ? v cc v xout drive capacity high i oh = -0.1 ma v cc - 0.5 ? v cc v drive capacity low i oh = -50 av cc - 0.5 ? v cc v v ol output ?l? voltage except p2_0 to p2_7, xout i ol = 1 ma ?? 0.5 v p2_0 to p2_7 drive capacity high i ol = 2 ma ?? 0.5 v drive capacity low i ol = 1 ma ?? 0.5 v xout drive capacity high i ol = 0.1 ma ?? 0.5 v drive capacity low i ol = 50 a ?? 0.5 v v t+- v t- hysteresis int0 , int1 , int2 , int3 , ki0 , ki1 , ki2 , ki3 , traio, rxd0, rxd1, clk0, clk1, ssi, scl, sda, sso 0.05 0.3 ? v reset 0.05 0.15 ? v i ih input ?h? current vi = 2.2 v ?? 4.0 a i il input ?l? current vi = 0 v ?? -4.0 a r pullup pull-up resistance vi = 0 v 100 200 600 k ? r fxin feedback resistance xin ? 5 ? m ? r fxcin feedback resistance xcin ? 35 ? m ? v ram ram hold voltage during stop mode 1.8 ?? v
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 48 of 51 rej03b0117-0300 table 5.29 electrical characteristics (6) [vcc = 2.2 v] (t opr = -20 to 85 c (n version) / -40 to 85 c (d version), unless otherwise specified.) symbol parameter condition standard unit min. typ. max. i cc power supply current (v cc = 2.2 to 2.7 v) single-chip mode, output pins are open, other pins are v ss high-speed clock mode xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz no division ? 3.5 ? ma xin = 5 mhz (square wave) high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma high-speed on- chip oscillator mode xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz no division ? 3.5 ? ma xin clock off high-speed on-chip oscillator on foco = 5 mhz low-speed on-chip oscillator on = 125 khz divide-by-8 ? 1.5 ? ma low-speed on- chip oscillator mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz divide-by-8, fmr47 = 1 ? 100 230 a low-speed clock mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz fmr47 = 1 ? 100 230 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz program operation on ram flash memory off, fmstp = 1 ? 25 ? a wait mode xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock operation vca27 = vca26 = vca25 = 0 vca20 = 1 ? 22 60 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator on = 125 khz while a wait instruction is executed peripheral clock off vca27 = vca26 = vca25 = 0 vca20 = 1 ? 20 55 a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (high drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 3.0 ? a xin clock off high-speed on-chip oscillator off low-speed on-chip oscillator off xcin clock oscillator on = 32 khz (low drive) while a wait instruction is executed vca27 = vca26 = vca25 = 0 vca20 = 1 ? 1.8 ? a increase during a/d converter operation without sample & hold ? 0.4 ? ma with sample & hold ? 0.3 ? ma stop mode xin clock off, t opr = 25 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 0.7 3.0 a xin clock off, t opr = 85 c high-speed on-chip oscillator off low-speed on-chip oscillator off cm10 = 1 peripheral clock off vca27 = vca26 = vca25 = 0 ? 1.1 ? a
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 49 of 51 rej03b0117-0300 timing requirements (unless otherwise specified: v cc = 2.2 v, v ss = 0 v at topr = 25 c) [v cc = 2.2 v] figure 5.16 xin input and xcin input timing diagram when v cc = 2.2 v figure 5.17 traio input timing diagram when v cc = 2.2 v table 5.30 xin input, xcin input symbol parameter standard unit min. max. t c(xin) xin input cycle time 200 ? ns t wh(xin) xin input ?h? width 90 ? ns t wl(xin) xin input ?l? width 90 ? ns t c(xcin) xcin input cycle time 14 ? s t wh(xcin) xcin input ?h? width 7 ? s t wl(xcin) xcin input ?l? width 7 ? s table 5.31 traio input symbol parameter standard unit min. max. t c(traio) traio input cycle time 500 ? ns t wh(traio) traio input ?h? width 200 ? ns t wl(traio) traio input ?l? width 200 ? ns xin input t wh(xin) t c(xin) t wl(xin) v cc = 2.2 v xcin input t wh(xcin) t c(xcin) t wl(xcin) traio input t c(traio) t wl(traio) t wh(traio) v cc = 2.2 v
r8c/24 group, r8c/25 group 5. electrical characteristics rev.3.00 feb 29, 2008 page 50 of 51 rej03b0117-0300 i = 0 or 1 figure 5.18 serial interface timing diagram when v cc = 2.2 v notes: 1. when selecting the digital filter by the inti input filter select bit, use an inti input high width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. 2. when selecting the digital filter by the inti input filter select bit, use an inti input low width of either (1/digital filter clock frequency 3) or the minimum value of standard, whichever is greater. figure 5.19 external interrupt inti input timing diagram when v cc = 2.2 v table 5.32 serial interface symbol parameter standard unit min. max. t c(ck) clki input cycle time 800 ? ns t w(ckh) clki input ?h? width 400 ? ns t w(ckl) clki input ?l? width 400 ? ns t d(c-q) txdi output delay time ? 200 ns t h(c-q) txdi hold time 0 ? ns t su(d-c) rxdi input setup time 150 ? ns t h(c-d) rxdi input hold time 90 ? ns table 5.33 external interrupt inti (i = 0 to 3) input symbol parameter standard unit min. max. t w(inh) int0 input ?h? width 1000 (1) ? ns t w(inl) int0 input ?l? width 1000 (2) ? ns t w(ckh) t c(ck) t w(ckl) t h(c-q) t h(c-d) t su(d-c) t d(c-q) clki txdi rxdi v cc = 2.2 v i = 0 or 1 inti input t w(inl) t w(inh) v cc = 2.2 v i = 0 to 3
rev.3.00 feb 29, 2008 page 51 of 51 rej03b0117-0300 r8c/24 group, r8c/25 group package dimensions package dimensions diagrams showing the latest package dimensions and mounti ng information are available in the ?packages? section of the renesas technology website. include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. detail f c a l1 l a2 a1 index mark x y * 3 * 1 * 2 f 39 27 13 1 40 52 26 14 zd ze d hd e he bp terminal cross section c bp c1 b1 previous code jeita package code renesas code plqp0052ja-a 52p6a-a mass[typ.] 0.3g p-lqfp52-10x10-0.65 1.0 0.125 0.30 1.1 1.1 0.13 0.20 0.145 0.09 0.37 0.32 0.27 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.65 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 e under development 0.15 v 0.20 w previous code jeita package code renesas code ptlg0064ja-a 64f0g mass[typ.] 0.07g p-tflga64-6x6-0.65 0.08 0.47 0.43 0.39 max nom min dimension in millimeters symbol reference 6.0 d 6.0 e 1.05 a x 0.65 e 0.10 y b 1 b 0.31 0.35 0.39 b w s w a s a h g f e d c b 12345678 s ys ab index mark sab v x4 (laser mark) index mark d e a b 1 b e e
a - 1 revision history r8c/24 group, r8c/25 group datasheet rev. date description page summary 0.01 sep 17, 2004 - first edition issued 0.02 dec 10, 2004 all pages part number revised. r8c/26 r8c/24, r8c/27 r8c/25 2, 3 table 1.1 r8c/24 group perf ormance, table 1.2 r8c/25 group performance - serial interface: i 2 c bus interface and chip-select clock synchronous (ssu) added. - lin module added. - interrupt: internal factors revised; 10 11 - note on operating ambient temperature added. 4 figure 1.1 block diagram - lin module added. - chip-select clock synchronous (ssu) is added to i 2 c bus interface. 5, 6 table 1.3 product information of r8c/24 group, table 1.4 product information of r8c/25 group date and development state revised. 7 figure 1.4 pin assignment p3_5/scl p3_5/scl/ssck, p3_3 p3_3/ssi, p3_4/sda p3_4/sda /scs , p3_7 p3_7/sso, vss/avss vss, xin/p4_6 p4_6/xin, vcc/avss vcc 12pin p1_7/traio/int1 to 22pin p1_0/ki0 /an8 20pin p1_7/traio/int1 to 30pin p1_0/ki0/an8 8 table 1.5 pin description - analog power supply input eliminated. - ssu added. 9 table 1.6 pin name information by pin number added. 15 table 4.1 sfr information (1) - 0031h: voltage detection register 1 voltage detection a register 1 - 0032h: voltage detection register 1 voltage detection a register 2 01000001b 001 00001b (note 4) - 0036h: ? (3) , 01000001b (4) ? eliminated. - 0038h: voltage monitor 0 control register (2) , vw0c, 00001000b (3) , 01000001b (4) added. 16 table 4.2 sfr information (2) - 0048h: timer rd0 interrupt control register, rd0ic, xxxxx000b added. - 0049h: timer rd interrupt control register, rdic timer rd1 interrupt control register, rd1ic - 004fh: iic interrupt control register, iic iic/ssu interrupt control register, iic2ic 19 table 4.5 sfr information (3) - 0106h: lin control register, lincr, 00h added. -0107h: lin status register, linst, 00h added. revision history r8c/24 group, r8c/25 group datasheet
a - 2 revision history r8c/24 group, r8c/25 group datasheet 0.10 feb 24, 2005 1 to 3 5, 6 pin type changed: 48-pin(under consideration) 52-pin. 5 to 7 package type revised: 48-pin lqfp (under consideration) plqp0052ja-a 8 table 1.5 tclk added, vref revised. 9 table 1.6 revised. 13, 14 figures 3.1 and 3.2 part number revised. 15 tabel 4.1 revised: - 000fh: 000xxxxxb 00011111b - 0023h: fr0 fra0 - 0024h: fr1 fra1 - 0025h: fr2 fra2 - 0031h: voltage detection a register 1, vc1 voltage detection register 1, vca1 - 0032h: voltage detection a register 2, vc2 voltage detection register 2, vca2 17 tabel 4.3 register name and the value after reset at 00b8h to 00bfh revised; note2 added. 19 tabel 4.5 revised: - 0107h: linsr linst - 0137h to 013fh: register symbol revised 20 tabel 4.6 revised: - 0140h to 015fh: register symbol revised - 0158h, 0159h: timer rd general register timer rd general register a1 0.20 mar 8, 2005 2, 3 8 tables 1.1, 1.2 and 1.5 revised: ?main clock? ?xin clock?; ?sub clock? ?xcin clock? 15 - 0023h to 0025h: 40mhz on-chip oscillator control register high-speed on-chip o scillator control register 0.30 sep 01, 2005 2, 3 table 1.1 r8c/24 group performance, table 1.2 r8c/25 group performance ? serial interface revised: - serial interface: 2 channels clock synchronous serial i/o, uart - clock synchronous serial interface: 1 channel i 2 c bus interface (1) , clock synchronous serial i/o with chip select 4 figure 1.1 block diagram ? uart or clock synchronous serial interface: ?(8 bits 1 channel)? ?(8 bits 2 channels)? revised ? uart (8 bits 1 channel) deleted 5, 6 table 1.3 product information of r8c/24 group, table 1.4 product information of r8c/25 group ?flash memory version? ?n version? revised rev. date description page summary
a - 3 revision history r8c/24 group, r8c/25 group datasheet 0.30 sep 01, 2005 7 figure 1.4 pin assignment ? pin name revised; vss vss/avss, vcc vcc/avcc, p1_5/rxd0/(traio)/(int1 ) p1_5/rxd0/(traio)/(int1 ) (2) , p6_6/int2 /(txd1) p6_6/int2 /txd1, p6_7/int3 /(rxd1) p6_7/int3 /rxd1, p6_5 p6_5/clk1 ? note2 added 8 table 1.5 pin description ? analog power supply input: line added ?int interrupt input: ?int0 timer rd input pins. int1 timer ra input pins.? added ? serial interface: ?clk1? added ??i 2 c bus interface (iic)? ?i 2 c bus interface? ? ?ssu? ?clock synchronous serial i/o with chip select? 9 table 1.6 pin name information by pin number revised ? pin number 10: ?vss? ?vss/avss? ? pin number 12: ?vcc? ?vcc/avcc? ?pin number 27: ?int0 ? added ? pin number 28: ?(txd1)? ?txd1? ? pin number 29: ?(rxd1)? ?rxd1? ? pin number 35: ?clk1? added 15 tabel 4.1 sfr information(1) revised: ? 0012h: x0h 00h ? 0013h: xxxxxx00b 00h ? 0016h: x0h 00h ? 0036h: voltage monitor 1 control register (2) voltage monitor 1 control register (5) ? 0038h: 00001000b (3) , 01000001b (4) 0000x000b (3) , 0100x001b (4) ? notes2, 5: ?the voltage monitor 1 reset? added ? note3: ?voltage monitor 1 reset? ?voltage monitor 0 reset? 16 tabel 4.2 sfr information(2) revised: ? 0048h: rd0ic trd0ic ? 0049h: rd1ic trd1ic ? 004ah: reic treic ? 004fh: ssu/iic interrupt control register, iic2aic ssu/iic interrupt control register (2) , ssuaic/iic2aic ? 0056h: raic traic ? 0058h: rbic trbic ? note2 added 17 tabel 4.3 sfr information(3) revised: ? 00bch: 00h 00h/0000x000b 18 tabel 4.4 sfr information(4) revised: ? 00d6h: 00000xxxb 00h ? 00f5h: uart1 function select register, u1sr, xxh added rev. date description page summary
a - 4 revision history r8c/24 group, r8c/25 group datasheet 0.30 sep 01, 2005 19 tabel 4.5 sfr information(5) revised: ? 0118h : timer re second data register/counter register timer re second data register/counter data register 20 tabel 4.6 sfr information(6) revised: ? 0145h pocr0 trdpocr0 ? 0146h, 0147h trdcnt0 trd0 ? 0148h, 0149h gra0 trdgra0 ? 014ah, 014bh grb0 trdgrb0 ? 014ch, 014dh grc0 trdgrc0 ? 014eh, 014fh grd0 trdgrd0 ? 0155h pocr1 trdpocr1 ? 0156h, 0157h trdcnt1 trd1 ? 0158h, 0159h gra1 trdgra1 ? 015ah, 015bh grb1 trdgrb1 ? 015ch, 015dh grc1 trdgrc1 ? 015eh, 015fh grd1 trdgrd1 21 tabel 4.7 sfr information(7) revised: ? 01b5h: 01000101b 1000000xb ? 01b7h: xx000001b 00000001b ? ffffh: (note 2) added 22 to 44 5. electrical characteristics added 0.40 jan 24, 2006 all pages ? ?preliminary? deleted ? symbol name ?trdmdr? ?trdmr?, ?ssuaic? ?ssuic?, and ?iic2aic? ?iicic? revised ? pin name ?tclk? ?trdclk? revised 2 table 1.1 functions and specific ations for r8c/24 group revised 3 table 1.2 functions and specific ations for r8c/25 group revised 4 figure 1.1 block diagram; ?peripheral functions? added, ?system clock generation? ?system clock ge nerator? revised 5 table 1.3 product information for r8c/24 group revised 6 table 1.4 product information for r8c/25 group revised 7 figure 1.4 pin assignments (top view) ?tclk? ?trdclk? revised 8 table 1.5 pin functions ?tclk? ?trdclk? revised 9 table 1.6 pin name information by pin number; ?tclk? ?trdclk? revised 10 figure 2.1 cpu registers; ?reserved area? ?reserved bit? revised 12 2.8.10 reserved area; ?reserved area? ?reserved bit? revised 13 figure 3.1 memory map of r8c/24 group; ?program area? ?program rom? revised 14 3.2 r8c/25 group, figure 3.2 memory map of r8c/25 group; ?data area? ?data flash?, ?program area? ?program rom? revised rev. date description page summary
a - 5 revision history r8c/24 group, r8c/25 group datasheet 0.40 jan 24, 2006 15 table 4.1 sfr information(1); 0024h: ?tbd? ?when shipping? notes 3 and 4 revised 19 table 4.5 sfr information (5); 0118h: ?timer re second data register? ?timer re second data register / counter data register? 0119h: ?timer re minute data register? ?timer re minute data register / compare data register? 0138h: ?trdmdr? ?trdmr? 013bh: ?timer rd output master enable register? ?timer rd output master enable register 1? 22 table 5.1 absolute maximum ratings; ?v cc ? ?v cc /av cc ? revised table 5.2 recommended operating conditions revised 23 table 5.3 a/d converter characteristics revised 24 table 5.4 flash memory (program rom) electrical characteristics revised 25 table 5.5 flash memory (data flash block a, block b) electrical revised 26 table 5.6 voltage detection 0 circui t electrical charac teristics revised table 5.7 voltage detection 1 circuit electrical charac teristics revised table 5.8 voltage detection 2 circuit electrical charac teristics revised 28 table 5.11 high-speed on-chip oscillator circuit electrical characteristics revised table 5.12 low-speed on-chip oscillator circuit electrical characteristics revised table 5.13 power supply circuit timing characteristics revised 29 table 5.14 timing requirements of clock synchronous serial i/o with chip select revised 33 table 5.15 timing requirements of i 2 c bus interface note1 revised 34 table 5.16 electrical characteristics (1) [v cc = 5 v] revised 35 table 5.17 electrical characteristics (2) [v cc = 5 v] revised 36 table 5.18 xin input, xcin input revised 37 table 5.20 serial interface revised 38 table 5.22 electrical characteristics (3) [v cc = 3 v] revised 39 table 5.23 electrical characte ristics (4) [vcc = 3 v] revised 40 table 5.24 xin input, xcin input revised 41 table 5.26 serial interface revised 42 table 5.28 electrical characteristics (5) [v cc = 2.2 v] revised 43 table 5.29 electrical characteristics (6) [vcc = 2.2 v] revised 44 table 5.30 xin input, xcin input revised table 5.31 traio input, int1 input revised 45 table 5.32 serial interface revised table 5.33 external interrupt inti (i = 0, 2, 3) input rev. date description page summary
a - 6 revision history r8c/24 group, r8c/25 group datasheet 0.40 jan 24, 2006 46 package dimensions; ?tbd? ?plqp0052ja-a (52p6a-a)? added 1.00 may 31, 2006 all pages ?under development? deleted 1 1. overview; ?data flash rom? ?data flash? revised 3 table 1.2 functions and specific ations for r8c/25 group revised 4 figure 1.1 block diagram; ?system clock generator? ?system clock generation circuit? revised 5 to 6 table 1.3 product information for r8c/24 group and table 1.4 product information for r8c/25 group; a part of (d) mark is deleted. 9 table 1.6 pin name information by pin number note1 added 15 table 4.1 sfr information(1); 001ch: ?00h? ?00h, 10000000b? revised 0029h: high-speed on-chip osci llator control register 4 fra4 when shipping added 002bh: high-speed on-chip os cillator control regist er 6 fra6 when shipping added note6 added 19 table 4.5 sfr information(5); 0118h: timer re second data regi ster / counter data register, 0119h: timer re minute data re gister / compare data register register name revised 20 table 4.6 sfr information(6); 0143h: ?11000000b? ?11100000b? revised 22 table 5.2 recommended operating conditions revised 24 table 5.4 flash memory (program rom) electrical characteristics revised 25 table 5.5 flash memory (data flash block a, block b) electrical characteristics revised 26 figure 5.2 time delay until suspend title revised 27 table 5.9 voltage monitor 0 reset electrical characteristics table 5.9 power-on reset circuit, voltage moni tor 0 reset electrica l characteristics revised table 5.10 power-on reset circuit electrical characteristics (when not using voltage monitor 0 reset) deleted figure 5.3 power-on reset circuit electrical characteristics revised 28 table 5.10 high-speed on-chip oscillator circuit electrical characteristics revised table 5.11 low-speed on-chip oscillator circuit electrical characteristics revised 35 table 5.16 electrical characte ristics (2) [vcc = 5 v] revised 39 table 5.22 electrical characte ristics (4) [vcc = 3 v] revised 43 table 5.28 electrical characteristics (6) [vcc = 2.2 v] revised 46 package dimensions; ?the latest package ... renesas technology website.? added rev. date description page summary
a - 7 revision history r8c/24 group, r8c/25 group datasheet 2.00 jul 14, 2006 all pages ?ptlg0064ja-a (64f0g)? package added 1 1. overview; ?... or a 64-pin molded-plastic flga.? added 2, 3 table 1.1 functions and specific ations for r8c/24 group, table 1.2 functions and specifications for r8c/25 group; package: ?64-pin molded-plastic flga? added 5 table 1.3 product information for r8c/24 group, figure 1.2 type number, memory size, and package of r8c/24 group revised 6 table 1.4 product information for r8c/25 group, figure 1.3 type number, memory size, and package of r8c/25 group revised 7 figure 1.4 plqp0052ja-a package pin assignments (top view); note3 revised 8 figure 1.5 ptlg0064ja-a package pin assignments added 14 figure 3.1 memory map of r8c/24 group revised 15 figure 3.2 memory map of r8c/25 group revised 23 table 5.1 absolute maximum ratings; note1 added 47 package dimensions; ?ptlg0064ja-a (64f0g)? added 3.00 feb 29, 2008 all pages y version added factory programming product added 2, 3 table 1.1, table 1.2 clock; ?real-time clock (timer re)? added 5, 7 table 1.3, table 1.4 revised 6, 8 figure 1.2, figure 1. 3; rom number ?xxx? added 16, 17 figure 3.1, figure 3.2; ?expanded area? deleted 18 table 4.1 revised 26 table 5.2 note2 revised 32 table 5.10; revised, note4 added table 5.11; oscillation stability time: condition ?v cc = 5.0 v, topr = 25c? deleted 38 table 5.15; i ih , i il , r pullup condition: ?vcc = 5v? added 39 table 5.16; condition: high-speed on-chip oscillator mode revised 40 table 5.17 added 41 figure 5.8 revised 43 table 5.22; i ih , i il , r pullup condition: ?vcc = 3v? added 44 table 5.23; condition ?increase duri ng a/d converter operation? added 45 figure 5.12 revised 48 table 5.29; condition ?increase duri ng a/d converter operation? added 49 figure 5.16 revised rev. date description page summary
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